Low power flip-flop with clock gating on master and slave latches - Electronics Letters
نویسنده
چکیده
I Conclusion: In this Letter, we have shown that the method proposed in [2] could be used even in the case where non-neglectible values of feedback delay are encountered. A very interesting conclusion is that an optimal gain margin may be reached with a nonzero value, i.e. a physical delay value. Furthermore, this delay (higher than one sampling period) allows for dynamic element matching techniques in the case of multibit modulators. Q
منابع مشابه
Asynchronous Model of Flip-Flop’s and Latches for Low Power Clocking
There is a wide selection of flip-flops in the literature. Many contemporary microprocessors selectively use master-slave and pulsed-triggered flip-flops. Transmission gated flip-flop, are made up of two stages, one master and one slave Alternatively, pulse-triggered flip-flops reduce the two stages into one stage and are characterized by the soft edge property. The concepts discussed in the re...
متن کاملComparative Analysis of Master–Slave Latches and Flip-Flops for High-Performance and Low-Power Systems
In this paper, we propose a set of rules for consistent estimation of the real performance and power features of the flip-flop and master–slave latch structures. A new simulation and optimization approach is presented, targeting both highperformance and power budget issues. The analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles. Cer...
متن کاملHigh-performance and Low-power Clock Branch Sharing Pseudo-NMOS Level Converting Flip-flop
Multi-Supply voltage design using Cluster Voltage Scaling (CVS) is an effective way to reduce power consumption without performance degradation. One of the major issues in this method is performance and power overheads due to insertion of Level Converting Flip-Flops (LCFF) at the interface from low-supply to high-supply clusters to simultaneously perform latching and level conversion. In this p...
متن کاملComparative analysis of Clock gated Data Look Ahead and Conditional Capture Flip-Flops and their area of Applications
Flip-Flops are off many types. Choosing the correct type FF for any application is very important to achieve high performance. the data look ahead d Flip-Flop (DLDFF) from the family of master-slave type is compared with pulse triggered conditional capture Flip-Flop(CCFF).The effect of clock gating on the performance of these Flip-Flops are analyzed. The two Flip-Flops are compared, with clock ...
متن کاملOptimization of CMOS Low Power High Speed Dual Edge Triggered Flip Flop
In recent years, there has been an increasing demand for high-speed digital circuits at low power consumption. The use of dual edge-triggered flip-flops can help reduce the clock frequency to half of the single edge-triggered flip-flops while maintaining the same data throughput, this thereafter translates to better performance in terms of both power dissipation and speed. Pulsetriggered flip-f...
متن کامل